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High-level synthesis (HLS), sometimes referred to as ''C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis'', is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior.〔Springer Book (High Level Synthesis From Algorithm to Digital Circuit ) ISBN 978-1-4020-8587-1〕 Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages.,〔IEEE Xplore (High-Level Synthesis: Past, Present, and Future ) DOI 10.1109/MDT.2009.83〕 although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/Matlab. The code is analyzed, architecturally constrained, and scheduled to create a register-transfer level (RTL) hardware description language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.〔EETimes (The 'why' and 'what' of algorithmic synthesis )〕 Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level. While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.〔 UBS University, France (C-Based Rapid Prototyping for Digital Signal Processing )〕 The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation. ==History== Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the FSM. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path. First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler〔BDTI (Architectural Design Of DSP ASICs: Tools And Techniques )〕 and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.〔EETimes (Behavioral synthesis crossroad )〕 In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behaviorial synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification.〔EETimes: (High-level synthesis rollouts enable ESL )〕 Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design. High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.〔SCDSource 2008 (ESL goes mainstream with synthesis, virtual platforms )〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「High-level synthesis」の詳細全文を読む スポンサード リンク
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